1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, more particularly, to a method of manufacturing a well pick-up structure of a non-volatile memory.
2. Description of Related Art
Non-volatile memory is a type of memory that has been widely used inside personal computer systems and electron equipments. Data can be stored, read out or erased from the non-volatile memory countless number of times and any stored data is retained even after power supplying the devices is cut off.
In general, the non-volatile memory cell is comprised of a stacked gate including a floating gate and a control gate made of doped polysilicon. The floating gate is disposed between the control gate and the substrate and in a floated state that is not electrically connected with any circuit. The control gate is electrically connected with the word line. In addition, a tunneling oxide layer is disposed between the substrate and the floating gate while an inter-gate dielectric layer is located between the floating gate and the control gate.
On the other hand, flash memory arrays that are often used in the manufacturing industries include NOR (Not-OR)-type and NAND (Not-AND)-type arrays. In the NAND-type array non-volatile memory structure, various memory cells are connected in series so as to provide a superior integrated density and area utilization compared with the NOR-type array non-volatile memory, and it has been widely used in various electronic products.
In the conventional NAND-type non-volatile memory, a cell well is disposed in the substrate. Because the resistance of the cell well is high, the device channel region has a poor conductivity, such that the device operating speed and the device performance are affected. Therefore, sufficient well pick-up structures are usually formed in the conventional NAND-type non-volatile memory to reduce the resistance of the well. For example, when the reading operation of the NAND non-volatile memory is performed, the well pick-up structure can maintain the cell well at a fine ground state to prevent the memory threshold voltage distribution from becoming wide. When the erasing operation for the NAND-type non-volatile memory is performed, the well pick-up structure can be used to rapidly charge the cell well to an erasing voltage (about 20 V) so as to increase the erasing speed.
Currently, there are two methods for forming the well pick-up structures. One method is that when defining the active region, a partial region along the extension direction of the active region in the memory array is remained to be a region for the well pick-up structure. Since this well pick-up structure is located in the memory array so that a partial area of the word line is occupied. Moreover, the region for the well pick-up structure has a width different from that of the word line. When defining the active region, the line widths are not uniform because of optical proximity effect. The masks for forming the word lines, bit line plugs and bit lines should be precisely adjusted, and thus the process window is reduced. The other method is that a partial region along the bit line between two memory arrays is remained to be a region for the well pick-up structure. Similarly, this well pick-up structure also occupies a partial area of the bit line, and the line widths are not uniform because of optical proximity effect, such that the process window is reduced.